library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;



entity framesend_unit IS
    GENERIC(
       num_requester      : natural := 4
    );
    PORT( 
       clk                : IN   std_logic;
       request            : IN   unsigned (num_requester-1 DOWNTO 0);
       in_to_send         : in   std_logic_vector((8*num_requester)-1 DOWNTO 0);
       fifo_halffull      : in   std_logic;
       write_enable       : in    std_logic_vector(num_requester-1 DOWNTO 0);
       
       schedule_nr_out    : out std_logic_vector (num_requester-1 DOWNTO 0);
       scheduling_done_out : out std_logic;
       
       read_enable        : out   std_logic;
       out_to_send        : out   std_logic_vector(7 DOWNTO 0);
       data_to_fifo_we    : out   std_logic
    );
end framesend_unit;



architecture Behavioral of framesend_unit is
 
  signal schedule_nr        : std_logic_vector (num_requester-1 DOWNTO 0);
  signal scheduling_done    : std_logic; 
  
  signal start_schedule     : std_logic;
  
  signal data_mux_tobuilder : std_logic_vector(7 DOWNTO 0);
 
  component arbiter IS
    GENERIC(
       num_requester      : natural := 4
    );
    PORT( 
       clk                : IN   std_logic;
       request            : IN   unsigned (num_requester-1 DOWNTO 0);
       start_schedule     : IN   std_logic;
       schedule_nr        : OUT   std_logic_vector (num_requester-1 DOWNTO 0);
       scheduling_done    : OUT   std_logic           
    );
  end component;
  
  
  component framebuilder_mux IS
    GENERIC(
       num_requester      : natural := 4
    );
    PORT( 
       in_to_send    : in std_logic_vector((8*num_requester)-1 DOWNTO 0);
       schedule_nr        : in   std_logic_vector (num_requester-1 DOWNTO 0);
       out_to_send     : out   std_logic_vector(7 DOWNTO 0)
    );
  end component;
  
  
  component framebuilder IS
    GENERIC(
       num_requester      : natural := 4
    );
    PORT( 
       clk                : IN    std_logic;
       grant_valid        : IN    std_logic;
       fifo_halffull      : in    std_logic;
       in_to_send         : in    std_logic_vector(7 DOWNTO 0); 
       write_enable       : in    std_logic_vector(num_requester-1 DOWNTO 0);
       read_enable        : out   std_logic;
       start_schedule     : out   std_logic; 
       out_to_send        : out   std_logic_vector(7 DOWNTO 0);
       data_to_fifo_we    : out   std_logic     
    );
   end component;
  
    
begin
  
    schedule_nr_out   <= schedule_nr;
    scheduling_done_out <= scheduling_done;
      
  
    arbiter1 : arbiter
    GENERIC map(
       num_requester     => num_requester
    )
    PORT map( 
       clk                => clk,
       request            => request,
       start_schedule     => start_schedule,
       schedule_nr        => schedule_nr,
       scheduling_done    => scheduling_done          
    );
    
    framebuilder_mux1 : framebuilder_mux
    GENERIC map(
       num_requester     => num_requester
    )
    PORT map( 
       in_to_send    =>  in_to_send,
       schedule_nr   =>  schedule_nr,
       out_to_send   =>  data_mux_tobuilder
    );
    
    framebuilder1 : framebuilder
    GENERIC map(
       num_requester     => num_requester
    )
    PORT map( 
       clk                => clk,
       grant_valid        => scheduling_done,
       fifo_halffull      => fifo_halffull,
       in_to_send         => data_mux_tobuilder,
       write_enable       => write_enable,
       read_enable        => read_enable,
       start_schedule     => start_schedule,
       out_to_send        => out_to_send,
       data_to_fifo_we    => data_to_fifo_we
    );
  


end Behavioral;












